IBM unveils world’s first sub-1nm chip with 100 billion transistors, cuts power use by 70%

For years, the semiconductor industry has lived with a looming question: what happens when chips get so small that shrinking them further stops making sense, or stops working at all? IBM says it has an answer.

On Thursday, the company introduced what it calls the world’s first sub-1-nanometer chip technology, built around a new 0.7-nm, or 7-angstrom, transistor node and a fresh chip architecture that IBM calls “nanostack.” The company says the experimental chip packs nearly 100 billion transistors into an area about the size of a fingernail, almost double the density of the 2 nm chip IBM revealed in 2021.

That matters for one reason above all: the old playbook for making chips faster and more efficient is getting harder to sustain. As transistors approach atomic-scale dimensions, the industry has had to find new ways to sustain performance gains without running headlong into the physical limits of silicon. IBM’s latest research is a sign that there may still be room left on that roadmap.

IBM says the new chip could deliver up to 50% higher performance or 70% better energy efficiency than its 2 nm node chips, depending on how designers choose to optimize the technology. If those gains hold up in future products, the implications stretch well beyond benchmark bragging rights. More efficient chips would matter for AI systems that consume enormous amounts of power, cloud infrastructure operators trying to squeeze more compute out of every rack, and consumer devices where battery life and heat still shape the user experience.

“IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow. “This industry-first innovation continues IBM’s legacy of leading in next-generation technologies and sets the foundation for the next era of computing.”

Nanostack, an Industry Breakthrough in Chip Design

At the center of the announcement is nanostack, a new transistor design IBM describes as the industry’s first known three-dimensional nanosheet-based architecture. Instead of continuing to squeeze more progress from a mostly two-dimensional layout, IBM’s researchers stacked and staggered transistors vertically. The idea is straightforward in theory and brutally hard in practice: use the third dimension to fit more transistor density into the same footprint, then tune different layers with different material combinations to independently improve performance and power characteristics.

IBM says it has already validated key parts of that architecture in the lab, including ultra-thin dielectric bonding in CMOS integration, dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance. In plain English, the company is arguing that nanostack is not just a concept sketch for a conference slide. It is a structure that can be physically built and can support real computation.

The company is pairing that architectural shift with memory improvements. In research presented at VLSI 2026, IBM said nanostack delivered 40% SRAM scaling, a notable step in a part of chip design that often becomes a bottleneck as AI workloads demand more bandwidth and faster data access. Memory may not grab headlines the way transistor counts do, but it plays a huge role in how well advanced chips actually perform in the real world.

IBM’s broader message is that chip scaling is not dead yet. The company says nanostack opens a path below the 1 nm node and could support at least another decade of semiconductor scaling. That is a bold claim at a time when each new process generation is more expensive, more complex, and harder to commercialize than the last.

It is worth separating what IBM announced today from what it did not announce. This is not a mass-market processor ready to ship in laptops or AI servers next quarter. It is a research milestone, the kind IBM has built a reputation around over the years. Big semiconductor breakthroughs often arrive first as proof-of-concept demonstrations long before they become production technology, if they make that leap at all. IBM is careful to frame nanostack as a path to future products, not as a finished commercial chip platform.

Still, IBM has a credible history in this corner of the industry. The company has spent decades on advanced semiconductor R&D and has leveraged its Albany, New York, research ecosystem to advance process technology, often in partnership with equipment and materials companies. IBM points to that track record in its latest announcement, linking the sub-1 nm chip to earlier milestones including its 2 nm node work and its broader efforts in silicon, AI hardware, and quantum processors.

That ecosystem is a big part of the story. IBM said its Albany research site will soon house a High Numerical Aperture Extreme Ultraviolet lithography tool from ASML, a critical piece of equipment for printing ever-smaller chip features. IBM says it has been working with partners, including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions, on the processes and tooling required for future sub-1 nm devices, and that the collaboration has already produced working devices.

The company is trying to position this announcement inside a bigger compute narrative, one that spans classical semiconductors, AI accelerators, and quantum hardware. IBM recently disclosed plans for Anderon, which it describes as the world’s first pure-play quantum foundry, meant to help scale quantum wafer manufacturing in the U.S. The sub-1 nm announcement does not directly alter that effort, but it reinforces the same message IBM has been pushing for years: it wants to be seen not just as an enterprise software company but as one of the few American firms still conducting foundational computing research at the transistor level.

The real test, of course, is whether nanostack can move from lab result to manufacturable process at a cost the industry can live with. That is where many promising chip ideas run into trouble. IBM says it sees a path to production in as little as five years. That timeline is ambitious, but not impossible if the process challenges, tooling, and partner ecosystem line up.

For now, the significance of the announcement is less about a chip you can buy and more about the signal it sends. IBM is betting that the next chapter of computing will not come from software alone. It will come from finding new ways to keep shrinking, stacking, and redesigning the hardware underneath AI, cloud infrastructure, and whatever comes after them.